gal20v8/883 high performance e 2 cmos pld generic array logic? 1 devices have been discontinued. features ? high performance e 2 cmos ? technology ? 10 ns maximum propagation delay ? fmax = 62.5 mhz ? 7 ns maximum from clock input to data output ? ttl compatible 12 ma outputs ? ultramos ? advanced cmos technology ? 50% reduction in power from bipolar ? 75ma typ icc on low power device ?e 2 cell technology ? reconfigurable logic ? reprogrammable cells ? 100% tested/100% yields ? high speed electrical erasure (<100ms) ? 20 year data retention ? eight output logic macrocells ? maximum flexibility for complex logic designs ? programmable output polarity ? also emulates 24-pin pal ? devices with full function/ fuse map/parametric compatibility ? preload and power-on reset of all registers ? 100% functional testability ? applications include: ? dma control ? state machine control ? high speed graphics processing ? standard logic speed upgrade ? electronic signature for identification description the gal20v8/883 is a high performance e 2 cmos program- mable logic devices processed in full compliance to mil-std- 883. this military grade device combines a high performance cmos process with electrically erasable (e 2 ) floating gate tech- nology to provide the highest speed/power performance available in the 883 qualified pld market. the generic gal architecture provides maximum design flexibil- ity by allowing the output logic macrocell (olmc) to be config- ured by the user. the gal20v8/883 is capable of emulating all standard 24-pin pal ? devices with full function/fuse map/para- metric compatibility. unique test circuitry and reprogrammable cells allow complete ac, dc, and functional testing during manufacture. therefore, lattice semiconductor delivers 100% field programmability and functionality of all gal products. in addition, 100 erase/write cycles and data retention in excess of 20 years are specified. 228 nc i/clk i i i i i i i nc nc nc gnd i i i/oe i i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q vcc i/o/q i i 4 5 7 9 11 12 14 16 18 19 21 23 25 26 gal20v8 top view lcc 1 12 13 24 i/clk i i i i i i i i i i gnd vcc i i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i i/oe 6 18 gal 20v8 cerdip copyright ? 2010 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. april 2010 tel. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com 20v8mil_04 functional block diagram pin configuration clk i i i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i i i i i i i i i i i/oe i/clk oe 8 8 8 8 8 8 8 8 olmc olmc olmc olmc olmc olmc olmc imux imux programmable and-array (64 x 40) olmc
specifications gal20v8b/883 2 devices have been discontinued. recommended operating conditions casetemperature (t c )............................... ?55 to 125 c supply voltage (v cc ) with respect to ground ..................... +4.50 to +5.50v absolute maximum ratings (1) supply voltage v cc ...................................... ?0.5 to +7v input voltage applied .......................... ?2.5 to v cc +1.0v off-state output voltage applied ......... ?2.5 to v cc +1.0v storage temperature ................................ ?65 to 150 c case temperature with power applied ........................................ ?55 to 125 c 1.stresses above those listed under the ?absolute maximum ratings? may cause permanent damage to the device. these are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). dc electrical characteristics over recommended operating conditions (unless otherwise specified) symbol parameter condition min. typ. 3 max. units v il input low voltage vss ? 0.5 ? 0.8 v v ih input high voltage 2.0 ? vcc+1 v i il input or i/o low leakage current 0v v in v il (max.) ? ? -100 a for -10 speed grade 1 input or i/o low leakage current 0v v in v il (max.) ? ? -10 a for -15 and -20 speed grades i ih input or i/o high leakage current 3.5 v ih v in v cc ??10 a v ol output low voltage i ol = max. v in = v il or v ih ? ? 0.5 v v oh output high voltage i oh = max. v in = v il or v ih 2.4 ? ? v i ol low level output current ? ? 12 ma i oh high level output current ? ? ?2.0 ma i os 2 output short circuit current v cc = 5v v out = 0.5v t a = 25 c ?30 ? ?150 ma i cc operating power v il = 0.5v v ih = 3.0v l -10/-15/-20 ? 75 130 ma supply current f toggle = 15mhz outputs open 1) the leakage current is due to the internal pull-up on all pins. see input buffer section for more information. 2) one output at a time for a maximum duration of one second. vout = 0.5v was selected to avoid test problems caused by tester ground degradation. characterized but not 100% tested. 3) typical values are at vcc = 5v and ta = 25 c
specifications gal20v8b/883 3 devices have been discontinued. -20 min. max. -15 min. max. -10 min. max. t pd a input or i/o to combinational output 2 10 2 15 2 20 ns t co a clock to output delay 1 7 1 12 1 15 ns t cf 2 ? clock to feedback delay ? 7 ? 12 ? 15 ns t su ? setup time, input or feedback before clock 10 ? 12 ? 15 ? ns t h ? hold time, input or feedback after clock 0? 0? 0 ?ns a maximum clock frequency with 58.8 ? 41.6 ? 33.3 ? mhz external feedback, 1/(tsu + tco) f max 3 a maximum clock frequency with 58.8 ? 41.6 ? 33.3 ? mhz internal feedback, 1/(tsu + tcf) a maximum clock frequency with 62.5 ? 50 ? 41.6 ? mhz no feedback t wh ? clock pulse duration, high 8 ? 10 ? 12 ? ns t wl ? clock pulse duration, low 8 ? 10 ? 12 ? ns t en b input or i/o to output enabled ? 10 ? 15 ? 20 ns b oe to output enabled ? 10 ? 15 ? 18 ns t dis c input or i/o to output disabled ? 10 ? 15 ? 20 ns c oe to output disabled ? 10 ? 15 ? 18 ns 1) refer to switching test conditions section. 2) calculated from f max with internal feedback. refer to fmax descriptions section. 3) refer to fmax descriptions section. ac switching characteristics over recommended operating conditions parameter units description test cond 1 . symbol parameter maximum* units test conditions c i input capacitance 10 pf v cc = 5.0v, v i = 2.0v c i/o i/o capacitance 10 pf v cc = 5.0v, v i/o = 2.0v *characterized but not 100% tested. capacitance (ta = 25 c, f = 1.0 mhz)
specifications gal20v8/883 4 devices have been discontinued. registered output combinatorial output oe to output enable/disable input or i/o to output enable/disable f max with feedback clock width combinational output valid input input or i/o feedback t pd combinational output input or i/o feedback t en t dis clk ( w/o fb ) 1/ f max t wl t wh input or i/o feedback registered output clk valid input (external fdbk) t su t co t h 1/ f max oe registered output t en t dis clk registered feedback t cf t su 1/ f max (internal fdbk) switching waveforms
specifications gal20v8/883 5 devices have been discontinued. f max with internal feedback 1/( t su+ t cf) note: t cf is a calculated value, derived by subtracting t su from the period of fmax w/internal feedback ( t cf = 1/ f max - t su). the value of t cf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. for example, the timing from clock to a combinatorial output is equal to t cf + t pd. f max with external feedback 1/( t su+ t co) note: f max with external feedback is calculated from measured t su and t co. f max with no feedback note: f max with no feedback may be less than 1/( t wh + t wl). this is to allow for a clock duty cycle of other than 50%. register logic array t co t su clk register logic array clk t su + t h clk register logic array t cf t pd input pulse levels gnd to 3.0v input rise and fall times 3ns 10% ? 90% input timing reference levels 1.5v output timing reference levels 1.5v output load see figure 3-state levels are measured 0.5v from steady-state active level. test point c * l from output (o/q) under test +5v *c l includes test fixture and probe capacitance r 2 r 1 fmax descriptions switching test conditions output load conditions (see figure) test condition r 1 r 2 c l a 390 750 50pf b active high 750 50pf active low 390 750 50pf c active high 750 5pf active low 390 750 5pf
specifications gal20v8/883 6 devices have been discontinued. note : lattice semiconductor recognizes the trend in military device procurement towards using smd compliant devices, as such, ordering by this number is recommended. gal20v8 ordering information (mil-std-883 and smd) part number description 1. discontinued per pcn #06-07. 2. discontinued per pcn #05a-10. # g n i r e d r o d p t ) s n () s n ( ) s n ( ) s n () s n ( u s t ) s n () s n ( ) s n ( ) s n () s n ( o c t ) s n () s n ( ) s n ( ) s n () s n ( c c i ) a m () a m ( ) a m ( ) a m () a m ( e g a k c a p3 8 8 - d t s - l i m# d m s 0 10 17 0 3 1p i d r e c n i p - 4 23 8 8 / d l 0 1 - b 8 v 0 2 l a g 2 a l 4 0 0 4 8 9 8 - 2 6 9 5 0 3 1c c l n i p - 8 23 8 8 / r l 0 1 - b 8 v 0 2 l a g 1 a 3 4 0 0 4 8 9 8 - 2 6 9 5 5 12 12 10 3 1p i d r e c n i p - 4 23 8 8 / d l 5 1 - b 8 v 0 2 l a g 2 a l 3 0 0 4 8 9 8 - 2 6 9 5 0 3 1c c l n i p - 8 23 8 8 / r l 5 1 - b 8 v 0 2 l a g 2 a 3 3 0 0 4 8 9 8 - 2 6 9 5 0 25 15 10 3 1p i d r e c n i p - 4 23 8 8 / d l 0 2 - b 8 v 0 2 l a g 2 a l 2 0 0 4 8 9 8 - 2 6 9 5 0 3 1c c l n i p - 8 23 8 8 / r l 0 2 - b 8 v 0 2 l a g 2 a 3 2 0 0 4 8 9 8 - 2 6 9 5
|
